Generally, integrated circuits (ICs) comprise individual devices, such as transistors, capacitors, or the like, formed on a substrate. One or more metal layers are then formed over the individual devices to provide connections between the individual devices and to provide connections to external devices. The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) are patterned in a wafer. FEOL generally covers everything up to (but not including) the deposition of metal layers. The back end of line (BEOL) is the second portion of IC fabrication where the individual devices get interconnected with wiring or metal layers on the wafer. BEOL generally begins when the first metal layer is deposited on the wafer. It includes contacts, insulating layers, metal layers, and bonding sites for chip-to-package connections.
The metal layers interconnecting individual devices typically comprise an inter-metal dielectric (IMD) layer in which interconnect structures, such as vias and conductive lines, are formed, through numerous and repetitive steps of deposition, patterning and etching of thin films on the surface of silicon wafer. Interconnections between different metal layers are made by vias, which go through insulating IMD layers separating metal layers and allow for communications between devices formed at metal layers to communicate with other devices in the metal layers or directly with the semiconductor devices in the substrate.
The IMD layers may be etched to create via openings, via holes, or trenches for conduction lines for metal layers. The etch process generally has certain over etch or under etch amount around the via openings, via holes, or trenches, due to overall process variation. It is possible that a via opening is over etched so that a via does not fully land on the under-layer metal, causing via to under-layer dielectric recess. It is also possible a via opening is not etched enough, causing via depth loading. Furthermore, a misplaced via may be risky for via to under-layer metal bridge causing circuit failure. New methods and apparatus are needed to avoid via to under-layer dielectric recess, via depth loading, and via to under-layer metal bridge issues.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.